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RNA52A10MM
Dual CMOS system-RESET IC
REJ03D0858-0400 Rev.4.00 Feb 23, 2007
Description
The RNA52A10MM incorporates two reset circuits, one with and one without a delay function, allowing the generation of separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset circuit is determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS process for the RNA52A10MM means that the device draws only 1.1 A (typ.). The reset cancellation delay time is set with a high degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR (manual reset) input pin is provided for the reset circuit with the delay function, and the reset signal is output in response to a high level on the MR input pin. The MR pin is pulled down by a 2-M internal resistor. Output pins Vo1 and Vo2 are open drain.
Features
* * * * * * * * * * Two CMOS reset circuits, one with and one without the delay function Reference voltage: 1.0 V Reference voltage accuracy: 50 mV Reference voltage hysteresis: 6% (typ.) Low current consumption: 1.1 A (typ.) Delay time set by an external CR circuit Manual reset input Open-drain output MMPAK-8 (8-pin) package Operating temperature range: - 40 to 85C
Pin Arrangement
MR Vo1 Vo2 GND 1 2 3 4 8 7 6 5 VDD Vi1 Vi2 CD
Application
* * * * * * * Power-supply monitoring and resetting for microprocessors Power supply sequence control for microprocessors Desktop and laptop PCs PC peripheral devices such as printers Digital still cameras, digital video cameras, and PDAs Battery-driven products Wireless communications systems
Rev.4.00
Feb 23, 2007
page 1 of 10
RNA52A10MM
Functional Block Diagram and Typical application Circuit
VDD3 VDD1 RS1 7 VDD4 RS2 VDD2 Reset circuit 2 RS3 6 RS4 VREF 1.0V 2M Vi2 RL2 Vo2 3 RESET Vi1 Reset circuit 1 Vo1 2 RL1
Microcomputer
8
VDD
1
MR
5
CD
GND
4
RD VDD0
CD
C1
Notes: 1. Please refer to the following equations to set up reset-threshold voltages for power supplies VDD1 and VDD2, and to set up external voltage-dividing resistor pairs RS1 and RS2, and RS3 and RS4. (1) VDD1 reset-threshold voltage = VREF x (RS1+RS2)/RS2 (2) VDD2 reset-threshold voltage = VREF x (RS3+RS4)/RS4 Note that values must be set up within the following range: RS1, RS2, RS3, RS4 50 k See the following graph for the relationship between the reference voltage variation and the value selected for RS1, RS2, RS3 and RS4. 2. For capacitor C1, select a type which has excellent frequency characteristics. For stable operation, place it between the VDD pin and the GND pin and as close as is possible to the chip. The value of capacitor C1 must suit the system environment in terms of the quality of the power supply and so forth.
Reference Voltage Variation vs. Parallel Resistance
Reference Voltage Variation [%]
5 4 3 2 1 0 -1 0.1 1 10 100 1000
Parallel Resistance (RS1//RS2, RS3//RS4) [k]
Rev.4.00
Feb 23, 2007
page 2 of 10
RNA52A10MM
Timing Diagram
1. I/O Table
MR L H Vi1, Vi2 VREF (VREF+VHYS) VREF (VREF+VHYS) Vo1 L H L H Vo2 L H (after TDLY0) L
2. Timing Chart
(VREF+VHYS) VREF (VREF+VHYS)
Vi1, Vi2
VDD0
MR
VDD3
Vo1
TDLY0 TDLY0 TDLY0 VDD4
Vo2
Absolute Maximum Ratings
Item Supply voltage (VDD) Input voltage (Vi1, Vi2, MR, CD) Output voltage (Vo1, Vo2) Output current (Vo1, Vo2) Symbol VDD VIN VOUT IOUT Ratings 6.0 -0.3 to VDD -0.3 to 6.0 30 145 Unit V V V mA mW C C
PD Continuous power dissipation (Ta = 25C, in still air) Operating temperature TOPR -40 to 85 Storage temperature TSTG -55 to 125 Note: Refer to the relevant characteristic curve on page 5 for continuous power dissipation.
Recommended Operating Conditions
Item Supply voltage (VDD) Input voltage (Vi1, Vi2, MR, CD) Output voltage (Vo1, Vo2) Output current (Vo1, Vo2) Operating temperature Symbol VDD VIN VOUT IOUT TOPR Min. 1.4 0 0 0 -40 Max. 5.5 VDD 5.5 15 85 Unit V V V mA C
Rev.4.00
Feb 23, 2007
page 3 of 10
RNA52A10MM
Electrical Characteristics
(Ta = 25C, unless otherwise noted)
Item Supply voltage Current consumption Reference voltage Reference voltage temperature coefficient (Reference value for design) Vi1, Vi2 input hysteresis voltage Vi1, Vi2 input current CD input threshold voltage Symbol VDD IDD VREF VREF VREF Ta Min. 1.4 -- 0.95 -- 28.5 (VREFx3%) -- VDDx0.43 Typ. -- 1.1 1.00 100 60 (VREFx6%) 0.6 VDDx0.63 Max. 5.5 19 1.05 -- 94.5 (VREFx9%) 2.2 VDDx0.83 Unit V A V ppm C Ta = -40 to 85C 2 VDD = 5.5 V Vi1 = V i2 = 5.5 V VDD = 3.3 V Test Conditions Test Circuit -- 1 2
VHYS IIN VDLY
mV A V
VDD = 3.3 V VDD = 5.5 V Vi1 = V i2 = 5.5 V VDD = 3.3 V Vi1 = V i2 = 1.2 V VDD = 1.4V Vi1 = V i2 = 0 V IOL = 0.5 mA VDD = 3.3V
2 3 4
-- Vo1, Vo2 low-level output voltage VOL -- Vo1, Vo2 output leakage current Incomplete discharge of capacity CD complete discharge of capacity CD
0.05
0.15
V
5
0.15
0.35
V
Vi1 = V i2 = 0 V IOL = 5 mA VDD = VO1 = VO2 = 5.5 V Vi1 = V i2 = 1.2 V
6
ILK
--
--
100
nA
7
TDLY
1.1
11
17
ms
Vo2 Note1 Delay time
VDD = 3.3 V Vi2 = 0 V1.2 V CD = 0.3 F, RD = 39 k
8
TDLY0
7
11
17
ms s
8
Vo1 Rise response time Vo1, Vo2 fall response time MR low-level input voltage VDD < 4.5V
TPLH
--
30
300
VDD = 3.3 V Vi1 = 0 V1.2 V VDD = 3.3 V Vi1 = Vi2 = 1.2 V0 V CD = 0.3 F, RD = 39 k VDD = 3.3 V Vi1 = V i2 = 1.2 V VDD = 3.3 V Vi1 = V i2 = 1.2 V VDD = 5.0 V Vi1 = V i2 = 1.2 V VDD = 5.5 V VMR = 5.5 V
9
TPHL
--
30
800
s
10
VIL
-- VDDx0.75
-- -- -- 2
VDDx0.2 -- -- --
V V V M
11 11 12 13
MR high-level input voltage
VIH VDD 4.5V RMR VDDx0.5 0.5
MR input pull-down resistance
Notes: 1. When capacitor CD is completely discharged and charging starts in the state that CD pin voltage is 0 V, the minimum value of delay time TDLY0 is 7 ms. However, when the discharging time is short and charging starts in the state that the voltage does not completely fall to 0 V, the minimum value of delay time TDLY is 1.1 ms. Then, the minimum value of Low time (reset time) of Vo2 is 1.1 ms as the delay time TDLY. Refer to Regulations for state of capacitor CD electrical discharge and delay time on page 9 for details. 2. Refer to the characteristic curves on page 5 for temperature dependence of the main characteristics. 3. Refer to pages 7 and 8 for the test circuits.
Rev.4.00
Feb 23, 2007
page 4 of 10
RNA52A10MM
Characteristic curves
Heat decrease curve
Current dissipation IDD [A] Power Dissipation PD [mW]
Current Dissipation IDD 20 15 10 VDD = 5.5 V, Vi1 = Vi2 = 5.5 V 5 0 -50
200 150 100 50 0 0 25 50 75 100 125 150 Ambient Temperature Ta [C]
-25
0
25
50
75
100
Ambient Temperature Ta [C]
Reference voltage VREF
Reference voltage VREF [V]
Vi1, Vi2 Input Current IIN 2.0
Input Current IIN [A]
1.04 1.02 VDD = 3.3 V 1.00 0.98 0.96 -50 -25 0 25 50 75 100 Ambient Temperature Ta [C]
1.5 1.0 0.5 0.0 -50 -25 0 25 50 75 100 Ambient Temperature Ta [C]
VDD = 5.5 V, Vi1 = Vi2 = 5.5 V
Vo1, Vo2 Low-level output voltage VOL
Low-level output voltage VOL [V]
Delay time TDLY0 20
Delay time TDLY0 [ms]
0.4 0.3 VDD = 3.3 V, IOL = 5 mA 0.2 0.1 0 -50
15 10 5 0 -50
VDD = 3.3 V, Vi2 = 0 to 1.2 V CD = 0.3 F, RD = 39 k
VDD = 1.4 V, IOL = 0.5 mA
-25
0
25
50
75
100
-25
0
25
50
75
100
Ambient Temperature Ta [C]
Ambient Temperature Ta [C]
Rise Response Time TPLH
Rise Response Time TPLH [ms] Fall Response Time TPHL [s]
Fall Response Time TPHL 1000 VDD = 3.3 V, Vi1 = Vi2 = 1.2 to 0 V CD = 0.3 F, RD = 39 K 100 Vi2 10 Vi1 1 -50
1000
100 VDD = 3.3 V, Vi1 = 0 to 1.2 V 10
1 -50
-25
0
25
50
75
100
-25
0
25
50
75
100
Ambient Temperature Ta [C]
Ambient Temperature Ta [C]
Rev.4.00
Feb 23, 2007
page 5 of 10
RNA52A10MM
Pin Descriptions
Pin No. Pin Name Function Manual reset input pin for reset circuit 2 (the circuit with the delay function). The MR signal is active high, so applying a high level to MR sets the Vo2 pin to the low level. 1 MR If Vi2 > VREF when the signal on the MR pin is changed back from the high to the low level, the Vo2 pin is returned from the low to the high level after a delay time TDLY0. This can be set as required. The MR pin is pulled down to the GND level via an internal 2-M resistor . However, we recommend connection of the pin to the GND line when it is not in use. Reset signal output pin for reset circuit 1 (the circuit with no delay function). The output is open-drain. The recommended value of the pull-up resistor (RL1) is 3 k to 100 k. When the voltage input on pin Vi1 falls 2 Vo1 to or below VREF, the signal output from the Vo1 pin is changed from the high to the low level. Since the characteristic includes hysteresis, the signal output from the Vo1 pin changes from the low to the high level when the voltage input on pin Vi1 rises to or above VREF+VHYS. Refer to the timing diagram on page 3 for details. Reset signal output pin for reset circuit 2 (the circuit with the delay function). The output is open-drain. The recommended value for the pull-up resistor (RL2 ) is 3 k to 100 k. When the voltage input on pin Vi2 falls to or below VREF, the signal output from the Vo2 pin is changed from the high to the low level. Since the input 3 Vo2 characteristic includes hysteresis, the signal output from the Vo2 pin changes from the low to the high level when the voltage input on pin Vi2 rises to or above VREF+VHYS and the set delay time TDLY0 has elapsed. Refer to the timing diagram on page 3 and regulations for state of capacitor CD electrical discharge and delay time on page 9 for details. 4 GND GND pin Pin for connection to the resistor (RD) and capacitor (CD) for setting of the delay time, TDLY0. Refer to the Block Diagram and Typical Application Circuit on page 2 for an example of the connection. The relation by which the resistance and capacitance set up the delay time can be expressed as TDLY0 = 0.94 x CD x RD. Refer to this 5 CD formula in determining the values of resistance and capacitance. Resistance RD must use the one within the range of 1 k to 1 M. Ensure that capacitor CD has a value no greater than 1.3 F. The dependence of delay time TDLY0 on the values of external capacitor CD and external resistor RD is illustrated on page 10. To avoid errors due to noise input via the CD pin, this input includes a Schmitt-trigger inverter. Voltage input pin for reset circuit 2 (the circuit with the delay function). When the input voltage falls to or below VREF, the signal output from the Vo2 pin is changed to the low level. Since the input characteristic includes hysteresis, the signal output from the Vo2 pin is changed from the low to the high level after the voltage input on pin Vi2 has risen to or above VREF+VHYS and delay time TDLY has elapsed. The reset-threshold voltage is 6 Vi2 derived from the power-supply voltage VDD2 according to the division ratio set up by resistors RS3 and RS4 as described under the block diagram and typical application circuit on page 2. To avoid shifting of the reset detection voltage being shifted by input current via the Vi2 pin, select a value no greater than 25 k for parallel resistors RS3 and RS4. Refer to the graph on page 2 for details. Besides, to avoid errors due to noise in power-supply voltage VDD2, select a capacitor with superior frequency characteristics and connect it between the Vi2 and GND pins. Voltage input pin for reset circuit 1 (the circuit without the delay function). When the input voltage falls to or below VREF, the signal output from the Vo1 pin is changed to the low level. Since the input characteristic includes hysteresis, the signal output from the Vo1 pin is changed from the low to the high level after the voltage input on pin Vi1 has risen to or above VREF+VHYS. The reset-threshold voltage is derived from the 7 Vi1 power-supply voltage VDD1 according to the division ratio set up by resistors RS1 and RS2 as described under the block diagram and typical application circuit on page 2. To avoid shifting of the reset detection voltage being shifted by input current via the Vi1 pin, select a value no greater than 25 k for parallel resistors RS1 and RS2. Refer to the graph on page 2 for details. Besides, to avoid errors due to noise in power-supply voltage VDD1, select a capacitor with superior frequency characteristics and connect it between the Vi2 and GND pins. Power-supply pin for the chip. For stable operation, select a capacitor with superior frequency characteristics 8 VDD and connect it between the VDD and GND pins and as close to the chip as possible. When selecting the value of the capacitor, consider aspects of the system environment such as the quality of the power supply. Refer to the block diagram and typical application circuit on page 2 for details.
Rev.4.00
Feb 23, 2007
page 6 of 10
RNA52A10MM
Test Circuits
1
100 k 100 k
2
100 k 39 k
A 1 MR VDD 8 Vi1 7 Vi2 6
0.3
100 k
1 MR
3.3 V
VDD 8 Vi1 7 Vi2 6
0.3
5.5 V
2 Vo1 3 Vo2 4 GND
2 Vo1 3 Vo2 4 GND
CD 5
5.5 V
CD 5
39 k
V
3
100 k 100 k
4
100 k 100 k
1 MR
5.5 V
VDD 8 Vi1 7 Vi2 6 CD 5
0.3
39 k
1 MR
3.3 V
VDD 8 Vi1 7 Vi2 6 CD 5 V
1.2 V 39 k 0.3 0V 3.3 V
2 Vo1 3 Vo2 4 GND
A A
5.5 V
2 Vo1 3 Vo2 4 GND
5
6
39k
1 MR
0.5 mA
VDD 8 Vi1 7 Vi2 6
1 MR
1.4 V
VDD 8 Vi1 7 Vi2 6 CD 5
2 Vo1 V 3 Vo2 4 GND V
2 Vo1
5 mA
V
3 Vo2 4 GND
0.5 mA
CD 5
0.3
0V
5 mA
V
7
A A 1 MR
5.5 V
VDD 8 Vi1 7 Vi2 6 CD 5
0.3
2 Vo1 3 Vo2 4 GND
39 k 1.2 V
Rev.4.00
Feb 23, 2007
page 7 of 10
RNA52A10MM
Test Circuits (cont.)
8
100 k 100 k 39 k
9
100 k 100 k
1 MR 2 Vo1 3 Vo2 4 GND
VDD 8 Vi1 7
1 MR 2 Vo1 3 Vo2 4 GND
VDD 8 Vi1 7 Vi2 6
0.3
3.3 V
0V
Vi2 6
0.3
3.3 V
39 k
CD 5
CD 5
3.3 V
3.3 V
Vi2
0V
1.06 V TDLY0 1.65 V 0V 3.3 V
Vi1
0V
1.06 V TPLH 1.65 V 0V 3.3 V
Vo2
Vo1
10
100 k 100 k
11
100 k 100 k
1 MR 2 Vo1 3 Vo2 4 GND
VDD 8 Vi1 7 Vi2 6
0.3
3.3 V
39 k
1 MR 2 Vo1 3 Vo2 4 GND
VDD 8 Vi1 7 Vi2 6 CD 5
0.3
39 k
0V 39 k 1.2 V 1.2 V 5.5 V 3.3 V
CD 5
3.3 V
Vi1, Vi2
3.3 V
1.0 V 0V TPHL 1.65V 0V
V
Vo1, Vo2
12
100 k 100 k
13
100 k 100 k
1 MR 2 Vo1 3 Vo2 4 GND V
VDD 8 Vi1 7 Vi2 6
39 k
1 MR
5.0 V
VDD 8 Vi1 7 Vi2 6
0.3
2 Vo1 3 Vo2
Rev.4.00
Feb 23, 2007
page 8 of 10
5.5 V
0.3
CD 5
1.2 V
A 4 GND CD 5
RNA52A10MM
Regulations for state of capacitor CD electrical discharge and delay time
(1) Operation to MR input signal
MR
Vth+
CD
VthCapacitor incomplete electrical discharge TDLY Vth-
Capacitor complete electrical discharge
Vth+
0V TDLY0
Vo2
(2) Operation to Vi2 input signal
Vi2
VREF
VREF+VHYS
VREF
VREF+VHYS
Vth+
CD
VthCapacitor incomplete electrical discharge TDLY Vth-
Capacitor complete electrical discharge
Vth+
0V TDLY0
Vo2
Rev.4.00
Feb 23, 2007
page 9 of 10
RNA52A10MM
Relation between Delay Time TDLY and External Component Values CD, RD
1000
Delay time TDLY0 [ms]
100
CD
=1
.0
F
.3 =0 3 F
CD
10
CD
.1 =0
F
.0 =0 33 F
CD
CD
1 1 10 Resistance RD [k] 100
.0 =0
1
F
1000
Package Dimensions
Package Name MMPAK-8 JEITA Package Code P-LSOP8-2.8 x 2.95 - 0.65 RENESAS Code PLSP0008JC-A Previous Code MASS[Typ.] 0.02 g
Unit: mm
0.13 +0.12 -0.03
2.95 0.2
4.0 0.3
2.8 0.1
0 to 0.1
0.65 1.95
0.1 M
0.2
1.1 0.1
0.3
0.1
Rev.4.00
Feb 23, 2007
page 10 of 10
0.6
+0.1 -0.05
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